early-access version 3045
This commit is contained in:
parent
d0429309af
commit
0af3e1b4e0
9 changed files with 179 additions and 172 deletions
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@ -1,7 +1,7 @@
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yuzu emulator early access
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=============
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This is the source code for early-access 3044.
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This is the source code for early-access 3045.
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## Legal Notice
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@ -117,12 +117,18 @@ void Maxwell3D::InitializeRegisterDefaults() {
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shadow_state = regs;
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inline_draw[MAXWELL3D_REG_INDEX(draw.end)] = true;
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inline_draw[MAXWELL3D_REG_INDEX(draw.begin)] = true;
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inline_draw[MAXWELL3D_REG_INDEX(vertex_buffer.first)] = true;
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inline_draw[MAXWELL3D_REG_INDEX(vertex_buffer.count)] = true;
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inline_draw[MAXWELL3D_REG_INDEX(index_buffer.first)] = true;
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inline_draw[MAXWELL3D_REG_INDEX(index_buffer.count)] = true;
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draw_command[MAXWELL3D_REG_INDEX(draw.end)] = true;
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draw_command[MAXWELL3D_REG_INDEX(draw.begin)] = true;
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draw_command[MAXWELL3D_REG_INDEX(vertex_buffer.first)] = true;
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draw_command[MAXWELL3D_REG_INDEX(vertex_buffer.count)] = true;
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draw_command[MAXWELL3D_REG_INDEX(index_buffer.first)] = true;
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draw_command[MAXWELL3D_REG_INDEX(index_buffer.count)] = true;
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draw_command[MAXWELL3D_REG_INDEX(index_buffer32_first)] = true;
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draw_command[MAXWELL3D_REG_INDEX(index_buffer16_first)] = true;
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draw_command[MAXWELL3D_REG_INDEX(index_buffer8_first)] = true;
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draw_command[MAXWELL3D_REG_INDEX(draw_inline_index)] = true;
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draw_command[MAXWELL3D_REG_INDEX(inline_index_2x16.even)] = true;
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draw_command[MAXWELL3D_REG_INDEX(inline_index_4x8.index0)] = true;
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}
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void Maxwell3D::ProcessMacro(u32 method, const u32* base_start, u32 amount, bool is_last_call) {
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@ -210,27 +216,6 @@ void Maxwell3D::ProcessMethodCall(u32 method, u32 argument, u32 nonshadow_argume
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return ProcessCBBind(3);
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case MAXWELL3D_REG_INDEX(bind_groups[4].raw_config):
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return ProcessCBBind(4);
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case MAXWELL3D_REG_INDEX(index_buffer32_first):
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regs.index_buffer.count = regs.index_buffer32_first.count;
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regs.index_buffer.first = regs.index_buffer32_first.first;
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dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
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draw_state.current_mode = DrawMode::Indexed;
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draw_state.gl_end_count = draw_state.instance_count = 1;
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return FlushInlineDraw();
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case MAXWELL3D_REG_INDEX(index_buffer16_first):
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regs.index_buffer.count = regs.index_buffer16_first.count;
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regs.index_buffer.first = regs.index_buffer16_first.first;
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dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
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draw_state.current_mode = DrawMode::Indexed;
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draw_state.gl_end_count = draw_state.instance_count = 1;
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return FlushInlineDraw();
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case MAXWELL3D_REG_INDEX(index_buffer8_first):
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regs.index_buffer.count = regs.index_buffer8_first.count;
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regs.index_buffer.first = regs.index_buffer8_first.first;
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dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
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draw_state.current_mode = DrawMode::Indexed;
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draw_state.gl_end_count = draw_state.instance_count = 1;
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return FlushInlineDraw();
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case MAXWELL3D_REG_INDEX(topology_override):
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use_topology_override = true;
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return;
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@ -265,9 +250,8 @@ void Maxwell3D::CallMacroMethod(u32 method, const std::vector<u32>& parameters)
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// Execute the current macro.
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macro_engine->Execute(macro_positions[entry], parameters);
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if (draw_state.current_mode != DrawMode::Undefined) {
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FlushInlineDraw();
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}
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ProcessDeferredDraw();
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}
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void Maxwell3D::CallMethod(u32 method, u32 method_argument, bool is_last_call) {
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@ -287,34 +271,28 @@ void Maxwell3D::CallMethod(u32 method, u32 method_argument, bool is_last_call) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid Maxwell3D register, increase the size of the Regs structure");
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if (inline_draw[method]) {
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if (draw_command[method]) {
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regs.reg_array[method] = method_argument;
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switch (method) {
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case MAXWELL3D_REG_INDEX(vertex_buffer.count):
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case MAXWELL3D_REG_INDEX(index_buffer.count): {
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const DrawMode expected_mode = method == MAXWELL3D_REG_INDEX(vertex_buffer.count)
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? DrawMode::Array
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: DrawMode::Indexed;
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StepInstance(expected_mode, method_argument);
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break;
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}
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case MAXWELL3D_REG_INDEX(draw.begin):
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draw_state.instance_mode =
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(regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::Subsequent) ||
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(regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::Unchanged);
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draw_state.gl_begin_consume = true;
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break;
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case MAXWELL3D_REG_INDEX(draw.end):
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draw_state.gl_end_count++;
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break;
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case MAXWELL3D_REG_INDEX(vertex_buffer.first):
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case MAXWELL3D_REG_INDEX(index_buffer.first):
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break;
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deferred_draw_method.push_back(method);
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auto u32_to_u8 = [&](const u32 argument) {
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inline_index_draw_indexes.push_back(static_cast<u8>(argument & 0x000000ff));
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inline_index_draw_indexes.push_back(static_cast<u8>((argument & 0x0000ff00) >> 8));
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inline_index_draw_indexes.push_back(static_cast<u8>((argument & 0x00ff0000) >> 16));
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inline_index_draw_indexes.push_back(static_cast<u8>((argument & 0xff000000) >> 24));
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};
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if (MAXWELL3D_REG_INDEX(draw_inline_index) == method) {
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u32_to_u8(method_argument);
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} else if (MAXWELL3D_REG_INDEX(inline_index_2x16.even) == method) {
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u32_to_u8(regs.inline_index_2x16.even);
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u32_to_u8(regs.inline_index_2x16.odd);
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} else if (MAXWELL3D_REG_INDEX(inline_index_4x8.index0) == method) {
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u32_to_u8(regs.inline_index_4x8.index0);
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u32_to_u8(regs.inline_index_4x8.index1);
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u32_to_u8(regs.inline_index_4x8.index2);
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u32_to_u8(regs.inline_index_4x8.index3);
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}
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} else {
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if (draw_state.current_mode != DrawMode::Undefined) {
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FlushInlineDraw();
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}
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ProcessDeferredDraw();
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const u32 argument = ProcessShadowRam(method, method_argument);
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ProcessDirtyRegisters(method, argument);
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@ -360,30 +338,6 @@ void Maxwell3D::CallMultiMethod(u32 method, const u32* base_start, u32 amount,
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}
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}
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void Maxwell3D::StepInstance(const DrawMode expected_mode, const u32 count) {
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if (draw_state.current_mode == DrawMode::Undefined) {
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if (draw_state.gl_begin_consume) {
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draw_state.current_mode = expected_mode;
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draw_state.current_count = count;
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draw_state.instance_count = 1;
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draw_state.gl_begin_consume = false;
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draw_state.gl_end_count = 0;
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}
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return;
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} else {
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if (draw_state.current_mode == expected_mode && count == draw_state.current_count &&
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draw_state.instance_mode && draw_state.gl_begin_consume) {
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draw_state.instance_count++;
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draw_state.gl_begin_consume = false;
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return;
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} else {
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FlushInlineDraw();
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}
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}
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// Tail call in case it needs to retry.
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StepInstance(expected_mode, count);
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}
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void Maxwell3D::ProcessTopologyOverride() {
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using PrimitiveTopology = Maxwell3D::Regs::PrimitiveTopology;
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using PrimitiveTopologyOverride = Maxwell3D::Regs::PrimitiveTopologyOverride;
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}
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}
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void Maxwell3D::FlushInlineDraw() {
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LOG_TRACE(HW_GPU, "called, topology={}, count={}", regs.draw.topology.Value(),
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regs.vertex_buffer.count);
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ASSERT_MSG(!(regs.index_buffer.count && regs.vertex_buffer.count), "Both indexed and direct?");
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ASSERT(draw_state.instance_count == draw_state.gl_end_count);
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// Both instance configuration registers can not be set at the same time.
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ASSERT_MSG(regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::First ||
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regs.draw.instance_id != Maxwell3D::Regs::Draw::InstanceId::Unchanged,
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"Illegal combination of instancing parameters");
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ProcessTopologyOverride();
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const bool is_indexed = draw_state.current_mode == DrawMode::Indexed;
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if (ShouldExecute()) {
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rasterizer->Draw(is_indexed);
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}
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// TODO(bunnei): Below, we reset vertex count so that we can use these registers to determine if
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// the game is trying to draw indexed or direct mode. This needs to be verified on HW still -
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// it's possible that it is incorrect and that there is some other register used to specify the
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// drawing mode.
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if (is_indexed) {
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regs.index_buffer.count = 0;
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} else {
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regs.vertex_buffer.count = 0;
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}
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draw_state.current_mode = DrawMode::Undefined;
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draw_state.current_count = 0;
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draw_state.instance_count = 0;
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draw_state.instance_mode = false;
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draw_state.gl_begin_consume = false;
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draw_state.gl_end_count = 0;
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}
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void Maxwell3D::ProcessMacroUpload(u32 data) {
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macro_engine->AddCode(regs.load_mme.instruction_ptr++, data);
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}
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@ -665,4 +583,95 @@ void Maxwell3D::ProcessClearBuffers() {
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rasterizer->Clear();
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}
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void Maxwell3D::ProcessDeferredDraw() {
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if (deferred_draw_method.empty()) {
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return;
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}
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enum class DrawMode {
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Undefined,
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General,
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Instance,
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};
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DrawMode draw_mode{DrawMode::Undefined};
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u32 instance_count = 1;
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auto first_method = deferred_draw_method[0];
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if (MAXWELL3D_REG_INDEX(draw.begin) == first_method) {
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// The minimum number of methods for drawing must be greater than or equal to
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// 3[draw.begin->vertex(index)count->draw.end] to avoid errors in index mode drawing
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if (deferred_draw_method.size() < 3) {
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return;
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}
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draw_mode = (regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::Subsequent) ||
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(regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::Unchanged)
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? DrawMode::Instance
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: DrawMode::General;
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} else if (MAXWELL3D_REG_INDEX(index_buffer32_first) == first_method ||
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MAXWELL3D_REG_INDEX(index_buffer16_first) == first_method ||
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MAXWELL3D_REG_INDEX(index_buffer8_first) == first_method) {
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draw_mode = DrawMode::General;
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}
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// Drawing will only begin with draw.begin or index_buffer method, other methods directly
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// clear
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if (draw_mode == DrawMode::Undefined) {
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deferred_draw_method.clear();
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return;
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}
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if (draw_mode == DrawMode::Instance) {
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ASSERT_MSG(deferred_draw_method.size() % 4 == 0, "Instance mode method size error");
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instance_count = static_cast<u32>(deferred_draw_method.size()) / 4;
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} else {
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if (MAXWELL3D_REG_INDEX(index_buffer32_first) == first_method) {
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regs.index_buffer.count = regs.index_buffer32_first.count;
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regs.index_buffer.first = regs.index_buffer32_first.first;
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dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
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} else if (MAXWELL3D_REG_INDEX(index_buffer32_first) == first_method) {
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regs.index_buffer.count = regs.index_buffer16_first.count;
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regs.index_buffer.first = regs.index_buffer16_first.first;
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dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
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} else if (MAXWELL3D_REG_INDEX(index_buffer32_first) == first_method) {
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regs.index_buffer.count = regs.index_buffer8_first.count;
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regs.index_buffer.first = regs.index_buffer8_first.first;
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dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
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} else {
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auto second_method = deferred_draw_method[1];
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if (MAXWELL3D_REG_INDEX(draw_inline_index) == second_method ||
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MAXWELL3D_REG_INDEX(inline_index_2x16.even) == second_method ||
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MAXWELL3D_REG_INDEX(inline_index_4x8.index0) == second_method) {
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regs.index_buffer.count = static_cast<u32>(inline_index_draw_indexes.size() / 4);
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regs.index_buffer.format = Regs::IndexFormat::UnsignedInt;
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}
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}
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}
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LOG_TRACE(HW_GPU, "called, topology={}, count={}", regs.draw.topology.Value(),
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regs.vertex_buffer.count);
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ASSERT_MSG(!(regs.index_buffer.count && regs.vertex_buffer.count), "Both indexed and direct?");
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// Both instance configuration registers can not be set at the same time.
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ASSERT_MSG(regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::First ||
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regs.draw.instance_id != Maxwell3D::Regs::Draw::InstanceId::Unchanged,
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"Illegal combination of instancing parameters");
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ProcessTopologyOverride();
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const bool is_indexed = regs.index_buffer.count && !regs.vertex_buffer.count;
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if (ShouldExecute()) {
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rasterizer->Draw(is_indexed, instance_count);
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}
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if (is_indexed) {
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regs.index_buffer.count = 0;
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} else {
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regs.vertex_buffer.count = 0;
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}
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deferred_draw_method.clear();
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inline_index_draw_indexes.clear();
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}
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} // namespace Tegra::Engines
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@ -1739,14 +1739,11 @@ public:
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Footprint_1x1_Virtual = 2,
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};
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struct InlineIndex4x8Align {
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struct InlineIndex4x8 {
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union {
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BitField<0, 30, u32> count;
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BitField<30, 2, u32> start;
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};
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};
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struct InlineIndex4x8Index {
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union {
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BitField<0, 8, u32> index0;
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BitField<8, 8, u32> index1;
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u32 depth_write_enabled; ///< 0x12E8
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u32 alpha_test_enabled; ///< 0x12EC
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INSERT_PADDING_BYTES_NOINIT(0x10);
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InlineIndex4x8Align inline_index_4x8_align; ///< 0x1300
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InlineIndex4x8Index inline_index_4x8_index; ///< 0x1304
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InlineIndex4x8 inline_index_4x8; ///< 0x1300
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D3DCullMode d3d_cull_mode; ///< 0x1308
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ComparisonOp depth_test_func; ///< 0x130C
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f32 alpha_test_ref; ///< 0x1310
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@ -3062,8 +3058,6 @@ public:
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void CallMultiMethod(u32 method, const u32* base_start, u32 amount,
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u32 methods_pending) override;
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void FlushInlineDraw();
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bool ShouldExecute() const {
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return execute_on;
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}
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@ -3076,21 +3070,6 @@ public:
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return *rasterizer;
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}
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enum class DrawMode : u32 {
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Undefined,
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Array,
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Indexed,
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};
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struct DrawState {
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DrawMode current_mode{DrawMode::Undefined};
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u32 current_count{};
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u32 instance_count{};
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bool instance_mode{};
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bool gl_begin_consume{};
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u32 gl_end_count{};
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} draw_state;
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struct DirtyState {
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using Flags = std::bitset<std::numeric_limits<u8>::max()>;
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using Table = std::array<u8, Regs::NUM_REGS>;
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@ -3100,6 +3079,8 @@ public:
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Tables tables{};
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} dirty;
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std::vector<u8> inline_index_draw_indexes;
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private:
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void InitializeRegisterDefaults();
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@ -3162,8 +3143,7 @@ private:
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/// Handles use of topology overrides (e.g., to avoid using a topology assigned from a macro)
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void ProcessTopologyOverride();
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// Handles a instance drawcall from MME
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void StepInstance(DrawMode expected_mode, u32 count);
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void ProcessDeferredDraw();
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/// Returns a query's value or an empty object if the value will be deferred through a cache.
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std::optional<u64> GetQueryResult();
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@ -3176,8 +3156,6 @@ private:
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/// Start offsets of each macro in macro_memory
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std::array<u32, 0x80> macro_positions{};
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std::array<bool, Regs::NUM_REGS> inline_draw{};
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/// Macro method that is currently being executed / being fed parameters.
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u32 executing_macro = 0;
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/// Parameters that have been submitted to the macro call so far.
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@ -3190,6 +3168,9 @@ private:
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bool execute_on{true};
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bool use_topology_override{false};
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std::array<bool, Regs::NUM_REGS> draw_command{};
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std::vector<u32> deferred_draw_method;
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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@ -3394,8 +3375,7 @@ ASSERT_REG_POSITION(alpha_to_coverage_dither, 0x12E0);
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ASSERT_REG_POSITION(blend_per_target_enabled, 0x12E4);
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ASSERT_REG_POSITION(depth_write_enabled, 0x12E8);
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ASSERT_REG_POSITION(alpha_test_enabled, 0x12EC);
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ASSERT_REG_POSITION(inline_index_4x8_align, 0x1300);
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ASSERT_REG_POSITION(inline_index_4x8_index, 0x1304);
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ASSERT_REG_POSITION(inline_index_4x8, 0x1300);
|
||||
ASSERT_REG_POSITION(d3d_cull_mode, 0x1308);
|
||||
ASSERT_REG_POSITION(depth_test_func, 0x130C);
|
||||
ASSERT_REG_POSITION(alpha_test_ref, 0x1310);
|
||||
|
|
|
@ -22,35 +22,29 @@ void HLE_771BB18C62444DA0(Engines::Maxwell3D& maxwell3d, const std::vector<u32>&
|
|||
maxwell3d.regs.draw.topology.Assign(
|
||||
static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[0] & 0x3ffffff));
|
||||
maxwell3d.regs.global_base_instance_index = parameters[5];
|
||||
maxwell3d.draw_state.instance_count = instance_count;
|
||||
maxwell3d.regs.global_base_vertex_index = parameters[3];
|
||||
maxwell3d.regs.index_buffer.count = parameters[1];
|
||||
maxwell3d.regs.index_buffer.first = parameters[4];
|
||||
|
||||
if (maxwell3d.ShouldExecute()) {
|
||||
maxwell3d.Rasterizer().Draw(true);
|
||||
maxwell3d.Rasterizer().Draw(true, instance_count);
|
||||
}
|
||||
maxwell3d.regs.index_buffer.count = 0;
|
||||
maxwell3d.draw_state.instance_count = 0;
|
||||
maxwell3d.draw_state.current_mode = Engines::Maxwell3D::DrawMode::Undefined;
|
||||
}
|
||||
|
||||
void HLE_0D61FC9FAAC9FCAD(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters) {
|
||||
const u32 count = (maxwell3d.GetRegisterValue(0xD1B) & parameters[2]);
|
||||
const u32 instance_count = (maxwell3d.GetRegisterValue(0xD1B) & parameters[2]);
|
||||
|
||||
maxwell3d.regs.vertex_buffer.first = parameters[3];
|
||||
maxwell3d.regs.vertex_buffer.count = parameters[1];
|
||||
maxwell3d.regs.global_base_instance_index = parameters[4];
|
||||
maxwell3d.regs.draw.topology.Assign(
|
||||
static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[0]));
|
||||
maxwell3d.draw_state.instance_count = count;
|
||||
|
||||
if (maxwell3d.ShouldExecute()) {
|
||||
maxwell3d.Rasterizer().Draw(false);
|
||||
maxwell3d.Rasterizer().Draw(false, instance_count);
|
||||
}
|
||||
maxwell3d.regs.vertex_buffer.count = 0;
|
||||
maxwell3d.draw_state.instance_count = 0;
|
||||
maxwell3d.draw_state.current_mode = Engines::Maxwell3D::DrawMode::Undefined;
|
||||
}
|
||||
|
||||
void HLE_0217920100488FF7(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters) {
|
||||
|
@ -63,39 +57,34 @@ void HLE_0217920100488FF7(Engines::Maxwell3D& maxwell3d, const std::vector<u32>&
|
|||
maxwell3d.dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
|
||||
maxwell3d.regs.global_base_vertex_index = element_base;
|
||||
maxwell3d.regs.global_base_instance_index = base_instance;
|
||||
maxwell3d.draw_state.instance_count = instance_count;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, element_base, true);
|
||||
maxwell3d.CallMethod(0x8e5, base_instance, true);
|
||||
maxwell3d.regs.draw.topology.Assign(
|
||||
static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[0]));
|
||||
if (maxwell3d.ShouldExecute()) {
|
||||
maxwell3d.Rasterizer().Draw(true);
|
||||
maxwell3d.Rasterizer().Draw(true, instance_count);
|
||||
}
|
||||
maxwell3d.regs.vertex_id_base = 0x0; // vertex id base?
|
||||
maxwell3d.regs.vertex_id_base = 0x0;
|
||||
maxwell3d.regs.index_buffer.count = 0;
|
||||
maxwell3d.regs.global_base_vertex_index = 0x0;
|
||||
maxwell3d.regs.global_base_instance_index = 0x0;
|
||||
maxwell3d.draw_state.instance_count = 0;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, 0x0, true);
|
||||
maxwell3d.CallMethod(0x8e5, 0x0, true);
|
||||
maxwell3d.draw_state.current_mode = Engines::Maxwell3D::DrawMode::Undefined;
|
||||
}
|
||||
|
||||
// Multidraw Indirect
|
||||
void HLE_3F5E74B9C9A50164(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters) {
|
||||
SCOPE_EXIT({
|
||||
// Clean everything.
|
||||
maxwell3d.regs.vertex_id_base = 0x0; // vertex id base?
|
||||
maxwell3d.regs.vertex_id_base = 0x0;
|
||||
maxwell3d.regs.index_buffer.count = 0;
|
||||
maxwell3d.regs.global_base_vertex_index = 0x0;
|
||||
maxwell3d.regs.global_base_instance_index = 0x0;
|
||||
maxwell3d.draw_state.instance_count = 0;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, 0x0, true);
|
||||
maxwell3d.CallMethod(0x8e5, 0x0, true);
|
||||
maxwell3d.draw_state.current_mode = Engines::Maxwell3D::DrawMode::Undefined;
|
||||
maxwell3d.dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
|
||||
});
|
||||
const u32 start_indirect = parameters[0];
|
||||
|
@ -127,15 +116,13 @@ void HLE_3F5E74B9C9A50164(Engines::Maxwell3D& maxwell3d, const std::vector<u32>&
|
|||
maxwell3d.regs.index_buffer.count = num_vertices;
|
||||
maxwell3d.regs.global_base_vertex_index = base_vertex;
|
||||
maxwell3d.regs.global_base_instance_index = base_instance;
|
||||
maxwell3d.draw_state.instance_count = instance_count;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, base_vertex, true);
|
||||
maxwell3d.CallMethod(0x8e5, base_instance, true);
|
||||
maxwell3d.dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
|
||||
if (maxwell3d.ShouldExecute()) {
|
||||
maxwell3d.Rasterizer().Draw(true);
|
||||
maxwell3d.Rasterizer().Draw(true, instance_count);
|
||||
}
|
||||
maxwell3d.draw_state.current_mode = Engines::Maxwell3D::DrawMode::Undefined;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -40,7 +40,7 @@ public:
|
|||
virtual ~RasterizerInterface() = default;
|
||||
|
||||
/// Dispatches a draw invocation
|
||||
virtual void Draw(bool is_indexed) = 0;
|
||||
virtual void Draw(bool is_indexed, u32 instance_count) = 0;
|
||||
|
||||
/// Clear the current framebuffer
|
||||
virtual void Clear() = 0;
|
||||
|
|
|
@ -205,7 +205,7 @@ void RasterizerOpenGL::Clear() {
|
|||
++num_queued_commands;
|
||||
}
|
||||
|
||||
void RasterizerOpenGL::Draw(bool is_indexed) {
|
||||
void RasterizerOpenGL::Draw(bool is_indexed, u32 instance_count) {
|
||||
MICROPROFILE_SCOPE(OpenGL_Drawing);
|
||||
|
||||
SCOPE_EXIT({ gpu.TickWork(); });
|
||||
|
@ -222,13 +222,15 @@ void RasterizerOpenGL::Draw(bool is_indexed) {
|
|||
pipeline->SetEngine(maxwell3d, gpu_memory);
|
||||
pipeline->Configure(is_indexed);
|
||||
|
||||
BindInlineIndexBuffer();
|
||||
|
||||
SyncState();
|
||||
|
||||
const GLenum primitive_mode = MaxwellToGL::PrimitiveTopology(maxwell3d->regs.draw.topology);
|
||||
BeginTransformFeedback(pipeline, primitive_mode);
|
||||
|
||||
const GLuint base_instance = static_cast<GLuint>(maxwell3d->regs.global_base_instance_index);
|
||||
const GLsizei num_instances = maxwell3d->draw_state.instance_count;
|
||||
const GLsizei num_instances = static_cast<GLsizei>(instance_count);
|
||||
if (is_indexed) {
|
||||
const GLint base_vertex = static_cast<GLint>(maxwell3d->regs.global_base_vertex_index);
|
||||
const GLsizei num_vertices = static_cast<GLsizei>(maxwell3d->regs.index_buffer.count);
|
||||
|
@ -1128,6 +1130,16 @@ void RasterizerOpenGL::ReleaseChannel(s32 channel_id) {
|
|||
query_cache.EraseChannel(channel_id);
|
||||
}
|
||||
|
||||
void RasterizerOpenGL::BindInlineIndexBuffer() {
|
||||
if (maxwell3d->inline_index_draw_indexes.empty()) {
|
||||
return;
|
||||
}
|
||||
const auto data_count = static_cast<u32>(maxwell3d->inline_index_draw_indexes.size());
|
||||
auto buffer = Buffer(buffer_cache_runtime, *this, 0, data_count);
|
||||
buffer.ImmediateUpload(0, maxwell3d->inline_index_draw_indexes);
|
||||
buffer_cache_runtime.BindIndexBuffer(buffer, 0, data_count);
|
||||
}
|
||||
|
||||
AccelerateDMA::AccelerateDMA(BufferCache& buffer_cache_) : buffer_cache{buffer_cache_} {}
|
||||
|
||||
bool AccelerateDMA::BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) {
|
||||
|
|
|
@ -68,7 +68,7 @@ public:
|
|||
StateTracker& state_tracker_);
|
||||
~RasterizerOpenGL() override;
|
||||
|
||||
void Draw(bool is_indexed) override;
|
||||
void Draw(bool is_indexed, u32 instance_count) override;
|
||||
void Clear() override;
|
||||
void DispatchCompute() override;
|
||||
void ResetCounter(VideoCore::QueryType type) override;
|
||||
|
@ -199,6 +199,8 @@ private:
|
|||
/// End a transform feedback
|
||||
void EndTransformFeedback();
|
||||
|
||||
void BindInlineIndexBuffer();
|
||||
|
||||
Tegra::GPU& gpu;
|
||||
|
||||
const Device& device;
|
||||
|
|
|
@ -174,7 +174,7 @@ RasterizerVulkan::RasterizerVulkan(Core::Frontend::EmuWindow& emu_window_, Tegra
|
|||
|
||||
RasterizerVulkan::~RasterizerVulkan() = default;
|
||||
|
||||
void RasterizerVulkan::Draw(bool is_indexed) {
|
||||
void RasterizerVulkan::Draw(bool is_indexed, u32 instance_count) {
|
||||
MICROPROFILE_SCOPE(Vulkan_Drawing);
|
||||
|
||||
SCOPE_EXIT({ gpu.TickWork(); });
|
||||
|
@ -191,12 +191,14 @@ void RasterizerVulkan::Draw(bool is_indexed) {
|
|||
pipeline->SetEngine(maxwell3d, gpu_memory);
|
||||
pipeline->Configure(is_indexed);
|
||||
|
||||
BindInlineIndexBuffer();
|
||||
|
||||
BeginTransformFeedback();
|
||||
|
||||
UpdateDynamicStates();
|
||||
|
||||
const auto& regs{maxwell3d->regs};
|
||||
const u32 num_instances{maxwell3d->draw_state.instance_count};
|
||||
const u32 num_instances{instance_count};
|
||||
const DrawParams draw_params{MakeDrawParams(regs, num_instances, is_indexed)};
|
||||
scheduler.Record([draw_params](vk::CommandBuffer cmdbuf) {
|
||||
if (draw_params.is_indexed) {
|
||||
|
@ -1006,4 +1008,17 @@ void RasterizerVulkan::ReleaseChannel(s32 channel_id) {
|
|||
query_cache.EraseChannel(channel_id);
|
||||
}
|
||||
|
||||
void RasterizerVulkan::BindInlineIndexBuffer() {
|
||||
if (maxwell3d->inline_index_draw_indexes.empty()) {
|
||||
return;
|
||||
}
|
||||
const auto data_count = static_cast<u32>(maxwell3d->inline_index_draw_indexes.size());
|
||||
auto buffer = buffer_cache_runtime.UploadStagingBuffer(data_count);
|
||||
std::memcpy(buffer.mapped_span.data(), maxwell3d->inline_index_draw_indexes.data(), data_count);
|
||||
buffer_cache_runtime.BindIndexBuffer(
|
||||
maxwell3d->regs.draw.topology, maxwell3d->regs.index_buffer.format,
|
||||
maxwell3d->regs.index_buffer.first, maxwell3d->regs.index_buffer.count, buffer.buffer,
|
||||
static_cast<u32>(buffer.offset), data_count);
|
||||
}
|
||||
|
||||
} // namespace Vulkan
|
||||
|
|
|
@ -64,7 +64,7 @@ public:
|
|||
StateTracker& state_tracker_, Scheduler& scheduler_);
|
||||
~RasterizerVulkan() override;
|
||||
|
||||
void Draw(bool is_indexed) override;
|
||||
void Draw(bool is_indexed, u32 instance_count) override;
|
||||
void Clear() override;
|
||||
void DispatchCompute() override;
|
||||
void ResetCounter(VideoCore::QueryType type) override;
|
||||
|
@ -141,6 +141,8 @@ private:
|
|||
|
||||
void UpdateVertexInput(Tegra::Engines::Maxwell3D::Regs& regs);
|
||||
|
||||
void BindInlineIndexBuffer();
|
||||
|
||||
Tegra::GPU& gpu;
|
||||
|
||||
ScreenInfo& screen_info;
|
||||
|
|
Loading…
Reference in a new issue