early-access version 1873

This commit is contained in:
pineappleEA 2021-07-13 04:45:17 +02:00
parent 9b2ef88b7d
commit 1ddc7f992d
16 changed files with 173 additions and 51 deletions

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@ -1,7 +1,7 @@
yuzu emulator early access yuzu emulator early access
============= =============
This is the source code for early-access 1871. This is the source code for early-access 1873.
## Legal Notice ## Legal Notice

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@ -29,6 +29,49 @@ IR::U1 IntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32
} }
} }
IR::U1 ExtendedIntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
CompareOp compare_op, bool is_signed) {
const IR::U32 zero{ir.Imm32(0)};
const IR::U32 carry{ir.Select(ir.GetCFlag(), ir.Imm32(1), zero)};
const IR::U1 z_flag{ir.GetZFlag()};
const IR::U32 intermediate{ir.IAdd(ir.IAdd(operand_1, ir.BitwiseNot(operand_2)), carry)};
const IR::U1 flip_logic{is_signed ? ir.Imm1(false)
: ir.LogicalXor(ir.ILessThan(operand_1, zero, true),
ir.ILessThan(operand_2, zero, true))};
switch (compare_op) {
case CompareOp::False:
return ir.Imm1(false);
case CompareOp::LessThan:
return IR::U1{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
ir.ILessThan(intermediate, zero, true))};
case CompareOp::Equal:
return ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag);
case CompareOp::LessThanEqual: {
const IR::U1 base_cmp{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
ir.ILessThan(intermediate, zero, true))};
return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
}
case CompareOp::GreaterThan: {
const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThanEqual(intermediate, zero, true),
ir.IGreaterThan(intermediate, zero, true))};
const IR::U1 not_z{ir.LogicalNot(z_flag)};
return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), not_z));
}
case CompareOp::NotEqual:
return ir.LogicalOr(ir.INotEqual(intermediate, zero),
ir.LogicalAnd(ir.IEqual(intermediate, zero), ir.LogicalNot(z_flag)));
case CompareOp::GreaterThanEqual: {
const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThan(intermediate, zero, true),
ir.IGreaterThanEqual(intermediate, zero, true))};
return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
}
case CompareOp::True:
return ir.Imm1(true);
default:
throw NotImplementedException("Invalid compare op {}", compare_op);
}
}
IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1, const IR::U1& predicate_2, IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1, const IR::U1& predicate_2,
BooleanOp bop) { BooleanOp bop) {
switch (bop) { switch (bop) {

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@ -11,6 +11,10 @@ namespace Shader::Maxwell {
[[nodiscard]] IR::U1 IntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1, [[nodiscard]] IR::U1 IntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1,
const IR::U32& operand_2, CompareOp compare_op, bool is_signed); const IR::U32& operand_2, CompareOp compare_op, bool is_signed);
[[nodiscard]] IR::U1 ExtendedIntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1,
const IR::U32& operand_2, CompareOp compare_op,
bool is_signed);
[[nodiscard]] IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1, [[nodiscard]] IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1,
const IR::U1& predicate_2, BooleanOp bop); const IR::U1& predicate_2, BooleanOp bop);

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@ -9,49 +9,6 @@
namespace Shader::Maxwell { namespace Shader::Maxwell {
namespace { namespace {
IR::U1 ExtendedIntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
CompareOp compare_op, bool is_signed) {
const IR::U32 zero{ir.Imm32(0)};
const IR::U32 carry{ir.Select(ir.GetCFlag(), ir.Imm32(1), zero)};
const IR::U1 z_flag{ir.GetZFlag()};
const IR::U32 intermediate{ir.IAdd(ir.IAdd(operand_1, ir.BitwiseNot(operand_2)), carry)};
const IR::U1 flip_logic{is_signed ? ir.Imm1(false)
: ir.LogicalXor(ir.ILessThan(operand_1, zero, true),
ir.ILessThan(operand_2, zero, true))};
switch (compare_op) {
case CompareOp::False:
return ir.Imm1(false);
case CompareOp::LessThan:
return IR::U1{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
ir.ILessThan(intermediate, zero, true))};
case CompareOp::Equal:
return ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag);
case CompareOp::LessThanEqual: {
const IR::U1 base_cmp{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
ir.ILessThan(intermediate, zero, true))};
return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
}
case CompareOp::GreaterThan: {
const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThanEqual(intermediate, zero, true),
ir.IGreaterThan(intermediate, zero, true))};
const IR::U1 not_z{ir.LogicalNot(z_flag)};
return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), not_z));
}
case CompareOp::NotEqual:
return ir.LogicalOr(ir.INotEqual(intermediate, zero),
ir.LogicalAnd(ir.IEqual(intermediate, zero), ir.LogicalNot(z_flag)));
case CompareOp::GreaterThanEqual: {
const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThan(intermediate, zero, true),
ir.IGreaterThanEqual(intermediate, zero, true))};
return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
}
case CompareOp::True:
return ir.Imm1(true);
default:
throw NotImplementedException("Invalid compare op {}", compare_op);
}
}
IR::U1 IsetCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2, IR::U1 IsetCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
CompareOp compare_op, bool is_signed, bool x) { CompareOp compare_op, bool is_signed, bool x) {
return x ? ExtendedIntegerCompare(ir, operand_1, operand_2, compare_op, is_signed) return x ? ExtendedIntegerCompare(ir, operand_1, operand_2, compare_op, is_signed)

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@ -9,6 +9,12 @@
namespace Shader::Maxwell { namespace Shader::Maxwell {
namespace { namespace {
IR::U1 IsetpCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
CompareOp compare_op, bool is_signed, bool x) {
return x ? ExtendedIntegerCompare(ir, operand_1, operand_2, compare_op, is_signed)
: IntegerCompare(ir, operand_1, operand_2, compare_op, is_signed);
}
void ISETP(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) { void ISETP(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
union { union {
u64 raw; u64 raw;
@ -17,15 +23,18 @@ void ISETP(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
BitField<8, 8, IR::Reg> src_reg_a; BitField<8, 8, IR::Reg> src_reg_a;
BitField<39, 3, IR::Pred> bop_pred; BitField<39, 3, IR::Pred> bop_pred;
BitField<42, 1, u64> neg_bop_pred; BitField<42, 1, u64> neg_bop_pred;
BitField<43, 1, u64> x;
BitField<45, 2, BooleanOp> bop; BitField<45, 2, BooleanOp> bop;
BitField<48, 1, u64> is_signed; BitField<48, 1, u64> is_signed;
BitField<49, 3, CompareOp> compare_op; BitField<49, 3, CompareOp> compare_op;
} const isetp{insn}; } const isetp{insn};
const bool is_signed{isetp.is_signed != 0};
const bool x{isetp.x != 0};
const BooleanOp bop{isetp.bop}; const BooleanOp bop{isetp.bop};
const CompareOp compare_op{isetp.compare_op}; const CompareOp compare_op{isetp.compare_op};
const IR::U32 op_a{v.X(isetp.src_reg_a)}; const IR::U32 op_a{v.X(isetp.src_reg_a)};
const IR::U1 comparison{IntegerCompare(v.ir, op_a, op_b, compare_op, isetp.is_signed != 0)}; const IR::U1 comparison{IsetpCompare(v.ir, op_a, op_b, compare_op, is_signed, x)};
const IR::U1 bop_pred{v.ir.GetPred(isetp.bop_pred, isetp.neg_bop_pred != 0)}; const IR::U1 bop_pred{v.ir.GetPred(isetp.bop_pred, isetp.neg_bop_pred != 0)};
const IR::U1 result_a{PredicateCombine(v.ir, comparison, bop_pred, bop)}; const IR::U1 result_a{PredicateCombine(v.ir, comparison, bop_pred, bop)};
const IR::U1 result_b{PredicateCombine(v.ir, v.ir.LogicalNot(comparison), bop_pred, bop)}; const IR::U1 result_b{PredicateCombine(v.ir, v.ir.LogicalNot(comparison), bop_pred, bop)};

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@ -186,11 +186,16 @@ public:
/// Pop asynchronous downloads /// Pop asynchronous downloads
void PopAsyncFlushes(); void PopAsyncFlushes();
[[nodiscard]] bool DMACopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount); bool DMACopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount);
bool DMAClear(GPUVAddr src_address, u64 amount, u32 value);
/// Return true when a CPU region is modified from the GPU /// Return true when a CPU region is modified from the GPU
[[nodiscard]] bool IsRegionGpuModified(VAddr addr, size_t size); [[nodiscard]] bool IsRegionGpuModified(VAddr addr, size_t size);
/// Return true when a region is registered on the cache
[[nodiscard]] bool IsRegionRegistered(VAddr addr, size_t size);
/// Return true when a CPU region is modified from the CPU /// Return true when a CPU region is modified from the CPU
[[nodiscard]] bool IsRegionCpuModified(VAddr addr, size_t size); [[nodiscard]] bool IsRegionCpuModified(VAddr addr, size_t size);
@ -516,8 +521,8 @@ bool BufferCache<P>::DMACopy(GPUVAddr src_address, GPUVAddr dest_address, u64 am
if (!cpu_src_address || !cpu_dest_address) { if (!cpu_src_address || !cpu_dest_address) {
return false; return false;
} }
const bool source_dirty = IsRegionGpuModified(*cpu_src_address, amount); const bool source_dirty = IsRegionRegistered(*cpu_src_address, amount);
const bool dest_dirty = IsRegionGpuModified(*cpu_dest_address, amount); const bool dest_dirty = IsRegionRegistered(*cpu_dest_address, amount);
if (!source_dirty && !dest_dirty) { if (!source_dirty && !dest_dirty) {
return false; return false;
} }
@ -562,7 +567,7 @@ bool BufferCache<P>::DMACopy(GPUVAddr src_address, GPUVAddr dest_address, u64 am
} }
runtime.CopyBuffer(dest_buffer, src_buffer, copies); runtime.CopyBuffer(dest_buffer, src_buffer, copies);
if (source_dirty) { if (IsRegionGpuModified(*cpu_src_address, amount)) {
dest_buffer.MarkRegionAsGpuModified(*cpu_dest_address, amount); dest_buffer.MarkRegionAsGpuModified(*cpu_dest_address, amount);
} }
std::vector<u8> tmp_buffer(amount); std::vector<u8> tmp_buffer(amount);
@ -571,6 +576,37 @@ bool BufferCache<P>::DMACopy(GPUVAddr src_address, GPUVAddr dest_address, u64 am
return true; return true;
} }
template <class P>
bool BufferCache<P>::DMAClear(GPUVAddr dst_address, u64 amount, u32 value) {
const std::optional<VAddr> cpu_dst_address = gpu_memory.GpuToCpuAddress(dst_address);
if (!cpu_dst_address) {
return false;
}
const bool dest_dirty = IsRegionRegistered(*cpu_dst_address, amount);
if (!dest_dirty) {
return false;
}
const IntervalType subtract_interval{*cpu_dst_address, *cpu_dst_address + amount * sizeof(u32)};
uncommitted_ranges.subtract(subtract_interval);
for (auto& interval_set : committed_ranges) {
interval_set.subtract(subtract_interval);
}
common_ranges.subtract(subtract_interval);
const size_t size = amount * sizeof(u32);
BufferId buffer;
do {
has_deleted_buffers = false;
buffer = FindBuffer(*cpu_dst_address, static_cast<u32>(size));
} while (has_deleted_buffers);
auto& dest_buffer = slot_buffers[buffer];
const u32 offset = static_cast<u32>(*cpu_dst_address - dest_buffer.CpuAddr());
runtime.ClearBuffer(dest_buffer, offset, size, value);
return true;
}
template <class P> template <class P>
void BufferCache<P>::BindGraphicsUniformBuffer(size_t stage, u32 index, GPUVAddr gpu_addr, void BufferCache<P>::BindGraphicsUniformBuffer(size_t stage, u32 index, GPUVAddr gpu_addr,
u32 size) { u32 size) {
@ -876,6 +912,27 @@ bool BufferCache<P>::IsRegionGpuModified(VAddr addr, size_t size) {
return false; return false;
} }
template <class P>
bool BufferCache<P>::IsRegionRegistered(VAddr addr, size_t size) {
const VAddr end_addr = addr + size;
const u64 page_end = Common::DivCeil(end_addr, PAGE_SIZE);
for (u64 page = addr >> PAGE_BITS; page < page_end;) {
const BufferId buffer_id = page_table[page];
if (!buffer_id) {
++page;
continue;
}
Buffer& buffer = slot_buffers[buffer_id];
const VAddr buf_start_addr = buffer.CpuAddr();
const VAddr buf_end_addr = buf_start_addr + buffer.SizeBytes();
if (buf_start_addr < end_addr && addr < buf_end_addr) {
return true;
}
page = Common::DivCeil(end_addr, PAGE_SIZE);
}
return false;
}
template <class P> template <class P>
bool BufferCache<P>::IsRegionCpuModified(VAddr addr, size_t size) { bool BufferCache<P>::IsRegionCpuModified(VAddr addr, size_t size) {
const u64 page_end = Common::DivCeil(addr + size, PAGE_SIZE); const u64 page_end = Common::DivCeil(addr + size, PAGE_SIZE);

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@ -87,8 +87,10 @@ void MaxwellDMA::CopyPitchToPitch() {
// TODO: allow multisized components. // TODO: allow multisized components.
if (is_buffer_clear) { if (is_buffer_clear) {
ASSERT(regs.remap_const.component_size_minus_one == 3); ASSERT(regs.remap_const.component_size_minus_one == 3);
accelerate.BufferClear(regs.offset_out, regs.line_length_in, regs.remap_consta_value);
std::vector<u32> tmp_buffer(regs.line_length_in, regs.remap_consta_value); std::vector<u32> tmp_buffer(regs.line_length_in, regs.remap_consta_value);
memory_manager.WriteBlock(regs.offset_out, reinterpret_cast<u8*>(tmp_buffer.data()), memory_manager.WriteBlockUnsafe(regs.offset_out,
reinterpret_cast<u8*>(tmp_buffer.data()),
regs.line_length_in * sizeof(u32)); regs.line_length_in * sizeof(u32));
return; return;
} }

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@ -31,6 +31,8 @@ class AccelerateDMAInterface {
public: public:
/// Write the value to the register identified by method. /// Write the value to the register identified by method.
virtual bool BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) = 0; virtual bool BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) = 0;
virtual bool BufferClear(GPUVAddr src_address, u64 amount, u32 value) = 0;
}; };
/** /**

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@ -145,6 +145,12 @@ void BufferCacheRuntime::CopyBuffer(Buffer& dst_buffer, Buffer& src_buffer,
} }
} }
void BufferCacheRuntime::ClearBuffer(Buffer& dest_buffer, u32 offset, size_t size, u32 value) {
glClearNamedBufferSubData(dest_buffer.Handle(), GL_R32UI, static_cast<GLintptr>(offset),
static_cast<GLsizeiptr>(size / sizeof(u32)), GL_RGBA, GL_UNSIGNED_INT,
&value);
}
void BufferCacheRuntime::BindIndexBuffer(Buffer& buffer, u32 offset, u32 size) { void BufferCacheRuntime::BindIndexBuffer(Buffer& buffer, u32 offset, u32 size) {
if (has_unified_vertex_buffers) { if (has_unified_vertex_buffers) {
buffer.MakeResident(GL_READ_ONLY); buffer.MakeResident(GL_READ_ONLY);

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@ -67,6 +67,8 @@ public:
void CopyBuffer(Buffer& dst_buffer, Buffer& src_buffer, void CopyBuffer(Buffer& dst_buffer, Buffer& src_buffer,
std::span<const VideoCommon::BufferCopy> copies); std::span<const VideoCommon::BufferCopy> copies);
void ClearBuffer(Buffer& dest_buffer, u32 offset, size_t size, u32 value);
void BindIndexBuffer(Buffer& buffer, u32 offset, u32 size); void BindIndexBuffer(Buffer& buffer, u32 offset, u32 size);
void BindVertexBuffer(u32 index, Buffer& buffer, u32 offset, u32 size, u32 stride); void BindVertexBuffer(u32 index, Buffer& buffer, u32 offset, u32 size, u32 stride);

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@ -1051,4 +1051,9 @@ bool AccelerateDMA::BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64
return buffer_cache.DMACopy(src_address, dest_address, amount); return buffer_cache.DMACopy(src_address, dest_address, amount);
} }
bool AccelerateDMA::BufferClear(GPUVAddr src_address, u64 amount, u32 value) {
std::scoped_lock lock{buffer_cache.mutex};
return buffer_cache.DMAClear(src_address, amount, value);
}
} // namespace OpenGL } // namespace OpenGL

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@ -63,6 +63,8 @@ public:
bool BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) override; bool BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) override;
bool BufferClear(GPUVAddr src_address, u64 amount, u32 value) override;
private: private:
BufferCache& buffer_cache; BufferCache& buffer_cache;
}; };

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@ -172,6 +172,30 @@ void BufferCacheRuntime::CopyBuffer(VkBuffer dst_buffer, VkBuffer src_buffer,
}); });
} }
void BufferCacheRuntime::ClearBuffer(VkBuffer dest_buffer, u32 offset, size_t size, u32 value) {
static constexpr VkMemoryBarrier READ_BARRIER{
.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
.pNext = nullptr,
.srcAccessMask = VK_ACCESS_MEMORY_WRITE_BIT,
.dstAccessMask = VK_ACCESS_TRANSFER_READ_BIT | VK_ACCESS_TRANSFER_WRITE_BIT,
};
static constexpr VkMemoryBarrier WRITE_BARRIER{
.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
.pNext = nullptr,
.srcAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT,
.dstAccessMask = VK_ACCESS_MEMORY_READ_BIT | VK_ACCESS_MEMORY_WRITE_BIT,
};
scheduler.RequestOutsideRenderPassOperationContext();
scheduler.Record([dest_buffer, offset, size, value](vk::CommandBuffer cmdbuf) {
cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT, VK_PIPELINE_STAGE_TRANSFER_BIT,
0, READ_BARRIER);
cmdbuf.FillBuffer(dest_buffer, offset, size, value);
cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_TRANSFER_BIT, VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
0, WRITE_BARRIER);
});
}
void BufferCacheRuntime::BindIndexBuffer(PrimitiveTopology topology, IndexFormat index_format, void BufferCacheRuntime::BindIndexBuffer(PrimitiveTopology topology, IndexFormat index_format,
u32 base_vertex, u32 num_indices, VkBuffer buffer, u32 base_vertex, u32 num_indices, VkBuffer buffer,
u32 offset, [[maybe_unused]] u32 size) { u32 offset, [[maybe_unused]] u32 size) {

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@ -72,6 +72,8 @@ public:
void CopyBuffer(VkBuffer src_buffer, VkBuffer dst_buffer, void CopyBuffer(VkBuffer src_buffer, VkBuffer dst_buffer,
std::span<const VideoCommon::BufferCopy> copies); std::span<const VideoCommon::BufferCopy> copies);
void ClearBuffer(VkBuffer dest_buffer, u32 offset, size_t size, u32 value);
void BindIndexBuffer(PrimitiveTopology topology, IndexFormat index_format, u32 num_indices, void BindIndexBuffer(PrimitiveTopology topology, IndexFormat index_format, u32 num_indices,
u32 base_vertex, VkBuffer buffer, u32 offset, u32 size); u32 base_vertex, VkBuffer buffer, u32 offset, u32 size);

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@ -541,6 +541,11 @@ void RasterizerVulkan::FlushWork() {
AccelerateDMA::AccelerateDMA(BufferCache& buffer_cache_) : buffer_cache{buffer_cache_} {} AccelerateDMA::AccelerateDMA(BufferCache& buffer_cache_) : buffer_cache{buffer_cache_} {}
bool AccelerateDMA::BufferClear(GPUVAddr src_address, u64 amount, u32 value) {
std::scoped_lock lock{buffer_cache.mutex};
return buffer_cache.DMAClear(src_address, amount, value);
}
bool AccelerateDMA::BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) { bool AccelerateDMA::BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) {
std::scoped_lock lock{buffer_cache.mutex}; std::scoped_lock lock{buffer_cache.mutex};
return buffer_cache.DMACopy(src_address, dest_address, amount); return buffer_cache.DMACopy(src_address, dest_address, amount);

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@ -55,6 +55,8 @@ public:
bool BufferCopy(GPUVAddr start_address, GPUVAddr end_address, u64 amount) override; bool BufferCopy(GPUVAddr start_address, GPUVAddr end_address, u64 amount) override;
bool BufferClear(GPUVAddr src_address, u64 amount, u32 value) override;
private: private:
BufferCache& buffer_cache; BufferCache& buffer_cache;
}; };