early-access version 3173
This commit is contained in:
parent
0b26e6367b
commit
37e45db751
13 changed files with 66 additions and 77 deletions
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@ -474,22 +474,7 @@ if (UNIX AND NOT APPLE)
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endif()
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if (NOT YUZU_USE_BUNDLED_FFMPEG)
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# Use system installed FFmpeg
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find_package(FFmpeg 4.3 QUIET COMPONENTS ${FFmpeg_COMPONENTS})
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if (FFmpeg_FOUND)
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# Overwrite aggregate defines from FFmpeg module to avoid over-linking libraries.
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# Prevents shipping too many libraries with the AppImage.
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set(FFmpeg_LIBRARIES "")
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set(FFmpeg_INCLUDE_DIR "")
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foreach(COMPONENT ${FFmpeg_COMPONENTS})
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set(FFmpeg_LIBRARIES ${FFmpeg_LIBRARIES} ${FFmpeg_LIBRARY_${COMPONENT}} CACHE PATH "Paths to FFmpeg libraries" FORCE)
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set(FFmpeg_INCLUDE_DIR ${FFmpeg_INCLUDE_DIR} ${FFmpeg_INCLUDE_${COMPONENT}} CACHE PATH "Path to FFmpeg headers" FORCE)
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endforeach()
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else()
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message(WARNING "FFmpeg not found or too old, falling back to externals")
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set(YUZU_USE_BUNDLED_FFMPEG ON)
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endif()
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find_package(FFmpeg 4.3 REQUIRED QUIET COMPONENTS ${FFmpeg_COMPONENTS})
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endif()
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# Prefer the -pthread flag on Linux.
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@ -1,7 +1,7 @@
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yuzu emulator early access
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=============
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This is the source code for early-access 3172.
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This is the source code for early-access 3173.
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## Legal Notice
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8
externals/find-modules/FindFFmpeg.cmake
vendored
8
externals/find-modules/FindFFmpeg.cmake
vendored
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@ -185,3 +185,11 @@ foreach(c ${_FFmpeg_ALL_COMPONENTS})
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endforeach()
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unset(_FFmpeg_ALL_COMPONENTS)
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unset(_FFmpeg_REQUIRED_VARS)
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include(FindPackageHandleStandardArgs)
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find_package_handle_standard_args(FFmpeg
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REQUIRED_VARS
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FFmpeg_LIBRARIES
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FFmpeg_INCLUDE_DIR
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HANDLE_COMPONENTS
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)
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@ -27,8 +27,6 @@ struct Program {
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u32 local_memory_size{};
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u32 shared_memory_size{};
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bool is_geometry_passthrough{};
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bool requires_layer_emulation{};
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Attribute emulated_layer{};
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};
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[[nodiscard]] std::string DumpProgram(const Program& program);
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@ -334,11 +334,11 @@ void ConvertLegacyToGeneric(IR::Program& program, const Shader::RuntimeInfo& run
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}
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}
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IR::Program GenerateLayerPassthrough(ObjectPool<IR::Inst>& inst_pool,
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ObjectPool<IR::Block>& block_pool,
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const HostTranslateInfo& host_info,
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IR::Program& source_program,
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Shader::OutputTopology output_topology) {
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IR::Program GenerateGeometryPassthrough(ObjectPool<IR::Inst>& inst_pool,
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ObjectPool<IR::Block>& block_pool,
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const HostTranslateInfo& host_info,
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IR::Program& source_program,
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Shader::OutputTopology output_topology) {
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IR::Program program;
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program.stage = Stage::Geometry;
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program.output_topology = output_topology;
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@ -357,8 +357,8 @@ IR::Program GenerateLayerPassthrough(ObjectPool<IR::Inst>& inst_pool,
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program.is_geometry_passthrough = false;
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program.info.loads.mask = source_program.info.stores.mask;
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program.info.stores.mask = source_program.info.stores.mask;
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program.info.stores.Set(IR::Attribute::Layer);
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program.info.stores.Set(source_program.emulated_layer, false);
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program.info.stores.Set(IR::Attribute::Layer, true);
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program.info.stores.Set(source_program.info.emulated_layer, false);
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IR::Block* current_block = block_pool.Create(inst_pool);
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auto& node{program.syntax_list.emplace_back()};
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@ -388,7 +388,7 @@ IR::Program GenerateLayerPassthrough(ObjectPool<IR::Inst>& inst_pool,
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ir.SetAttribute(attr + 3, ir.GetAttribute(attr + 3, ir.Imm32(i)), ir.Imm32(0));
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// Assign layer
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ir.SetAttribute(IR::Attribute::Layer, ir.GetAttribute(source_program.emulated_layer),
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ir.SetAttribute(IR::Attribute::Layer, ir.GetAttribute(source_program.info.emulated_layer),
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ir.Imm32(0));
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// Emit vertex
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@ -28,10 +28,10 @@ void ConvertLegacyToGeneric(IR::Program& program, const RuntimeInfo& runtime_inf
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// Maxwell v1 and older Nvidia cards don't support setting gl_Layer from non-geometry stages.
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// This creates a workaround by setting the layer as a generic output and creating a
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// passthrough geometry shader that reads the generic and sets the layer.
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[[nodiscard]] IR::Program GenerateLayerPassthrough(ObjectPool<IR::Inst>& inst_pool,
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ObjectPool<IR::Block>& block_pool,
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const HostTranslateInfo& host_info,
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IR::Program& source_program,
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Shader::OutputTopology output_topology);
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[[nodiscard]] IR::Program GenerateGeometryPassthrough(ObjectPool<IR::Inst>& inst_pool,
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ObjectPool<IR::Block>& block_pool,
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const HostTranslateInfo& host_info,
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IR::Program& source_program,
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Shader::OutputTopology output_topology);
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} // namespace Shader::Maxwell
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@ -13,8 +13,8 @@ struct HostTranslateInfo {
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bool support_float16{}; ///< True when the device supports 16-bit floats
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bool support_int64{}; ///< True when the device supports 64-bit integers
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bool needs_demote_reorder{}; ///< True when the device needs DemoteToHelperInvocation reordered
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bool support_snorm_render_buffer{}; ///< True when the device supports SNORM render buffers
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bool requires_layer_emulation{}; ///< True when the device doesn't support gl_Layer in VS
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bool support_snorm_render_buffer{}; ///< True when the device supports SNORM render buffers
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bool support_viewport_index_layer{}; ///< True when the device supports gl_Layer in VS
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};
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} // namespace Shader
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@ -39,12 +39,12 @@ static bool PermittedProgramStage(Stage stage) {
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}
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void LayerPass(IR::Program& program, const HostTranslateInfo& host_info) {
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if (!host_info.requires_layer_emulation || !PermittedProgramStage(program.stage)) {
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if (host_info.support_viewport_index_layer || !PermittedProgramStage(program.stage)) {
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return;
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}
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const auto end{program.post_order_blocks.end()};
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const auto emulated_layer = EmulatedLayerAttribute(program.info.stores);
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const auto layer_attribute = EmulatedLayerAttribute(program.info.stores);
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bool requires_layer_emulation = false;
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for (auto block = program.post_order_blocks.begin(); block != end; ++block) {
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if (inst.GetOpcode() == IR::Opcode::SetAttribute &&
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inst.Arg(0).Attribute() == IR::Attribute::Layer) {
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requires_layer_emulation = true;
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inst.SetArg(0, IR::Value{emulated_layer});
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inst.SetArg(0, IR::Value{layer_attribute});
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}
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}
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}
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if (requires_layer_emulation) {
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program.requires_layer_emulation = true;
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program.emulated_layer = emulated_layer;
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program.info.requires_layer_emulation = true;
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program.info.emulated_layer = layer_attribute;
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program.info.stores.Set(IR::Attribute::Layer, false);
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program.info.stores.Set(emulated_layer, true);
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program.info.stores.Set(layer_attribute, true);
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}
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}
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@ -204,6 +204,9 @@ struct Info {
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u32 nvn_buffer_base{};
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std::bitset<16> nvn_buffer_used{};
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bool requires_layer_emulation{};
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IR::Attribute emulated_layer{};
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boost::container::static_vector<ConstantBufferDescriptor, MAX_CBUFS>
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constant_buffer_descriptors;
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boost::container::static_vector<StorageBufferDescriptor, MAX_SSBOS> storage_buffers_descriptors;
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@ -126,7 +126,6 @@ void Maxwell3D::InitializeRegisterDefaults() {
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draw_command[MAXWELL3D_REG_INDEX(draw_inline_index)] = true;
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draw_command[MAXWELL3D_REG_INDEX(inline_index_2x16.even)] = true;
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draw_command[MAXWELL3D_REG_INDEX(inline_index_4x8.index0)] = true;
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draw_command[MAXWELL3D_REG_INDEX(draw.instance_id)] = true;
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}
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void Maxwell3D::ProcessMacro(u32 method, const u32* base_start, u32 amount, bool is_last_call) {
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regs.index_buffer.count = regs.index_buffer32_first.count;
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regs.index_buffer.first = regs.index_buffer32_first.first;
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dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
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draw_indexed = true;
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return ProcessDraw();
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case MAXWELL3D_REG_INDEX(index_buffer16_first):
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regs.index_buffer.count = regs.index_buffer16_first.count;
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regs.index_buffer.first = regs.index_buffer16_first.first;
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dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
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draw_indexed = true;
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return ProcessDraw();
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case MAXWELL3D_REG_INDEX(index_buffer8_first):
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regs.index_buffer.count = regs.index_buffer8_first.count;
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regs.index_buffer.first = regs.index_buffer8_first.first;
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dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
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draw_indexed = true;
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return ProcessDraw();
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case MAXWELL3D_REG_INDEX(topology_override):
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use_topology_override = true;
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draw_mode = DrawMode::InlineIndex;
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};
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switch (method) {
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case MAXWELL3D_REG_INDEX(draw.begin): {
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draw_mode =
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(regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::Subsequent) ||
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(regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::Unchanged)
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? DrawMode::Instance
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: DrawMode::General;
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break;
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}
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case MAXWELL3D_REG_INDEX(draw.end):
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switch (draw_mode) {
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case DrawMode::General:
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ProcessDraw(1);
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ProcessDraw();
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break;
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case DrawMode::InlineIndex:
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regs.index_buffer.count = static_cast<u32>(inline_index_draw_indexes.size() / 4);
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regs.index_buffer.format = Regs::IndexFormat::UnsignedInt;
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ProcessDraw(1);
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draw_indexed = true;
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ProcessDraw();
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inline_index_draw_indexes.clear();
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break;
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case DrawMode::Instance:
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break;
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}
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break;
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case MAXWELL3D_REG_INDEX(index_buffer.count):
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draw_indexed = true;
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break;
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case MAXWELL3D_REG_INDEX(draw_inline_index):
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update_inline_index(method_argument);
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break;
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update_inline_index(regs.inline_index_4x8.index2);
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update_inline_index(regs.inline_index_4x8.index3);
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break;
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case MAXWELL3D_REG_INDEX(draw.instance_id):
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draw_mode =
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(regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::Subsequent) ||
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(regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::Unchanged)
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? DrawMode::Instance
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: DrawMode::General;
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break;
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}
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} else {
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ProcessDeferredDraw();
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void Maxwell3D::ProcessDraw(u32 instance_count) {
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LOG_TRACE(HW_GPU, "called, topology={}, count={}", regs.draw.topology.Value(),
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regs.vertex_buffer.count);
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ASSERT_MSG(!(regs.index_buffer.count && regs.vertex_buffer.count), "Both indexed and direct?");
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// Both instance configuration registers can not be set at the same time.
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ASSERT_MSG(regs.draw.instance_id == Maxwell3D::Regs::Draw::InstanceId::First ||
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regs.draw.instance_id != Maxwell3D::Regs::Draw::InstanceId::Unchanged,
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"Illegal combination of instancing parameters");
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draw_indexed ? regs.index_buffer.count : regs.vertex_buffer.count);
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ProcessTopologyOverride();
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const bool is_indexed = regs.index_buffer.count && !regs.vertex_buffer.count;
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if (ShouldExecute()) {
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rasterizer->Draw(is_indexed, instance_count);
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rasterizer->Draw(draw_indexed, instance_count);
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}
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if (is_indexed) {
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regs.index_buffer.count = 0;
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} else {
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regs.vertex_buffer.count = 0;
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}
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draw_indexed = false;
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deferred_draw_method.clear();
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}
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void Maxwell3D::ProcessDeferredDraw() {
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@ -667,8 +663,6 @@ void Maxwell3D::ProcessDeferredDraw() {
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ASSERT_MSG(!(vertex_buffer_count && index_buffer_count), "Instance both indexed and direct?");
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ProcessDraw(instance_count);
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deferred_draw_method.clear();
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}
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} // namespace Tegra::Engines
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@ -3159,6 +3159,7 @@ private:
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std::vector<u32> deferred_draw_method;
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enum class DrawMode : u32 { General = 0, Instance, InlineIndex };
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DrawMode draw_mode{DrawMode::General};
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bool draw_indexed{};
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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@ -39,7 +39,7 @@ using Shader::Backend::GLASM::EmitGLASM;
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using Shader::Backend::GLSL::EmitGLSL;
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using Shader::Backend::SPIRV::EmitSPIRV;
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using Shader::Maxwell::ConvertLegacyToGeneric;
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using Shader::Maxwell::GenerateLayerPassthrough;
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using Shader::Maxwell::GenerateGeometryPassthrough;
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using Shader::Maxwell::MergeDualVertexPrograms;
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using Shader::Maxwell::TranslateProgram;
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using VideoCommon::ComputeEnvironment;
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@ -232,7 +232,7 @@ ShaderCache::ShaderCache(RasterizerOpenGL& rasterizer_, Core::Frontend::EmuWindo
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.support_int64 = device.HasShaderInt64(),
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.needs_demote_reorder = device.IsAmd(),
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.support_snorm_render_buffer = false,
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.requires_layer_emulation = !device.HasVertexViewportLayer(),
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.support_viewport_index_layer = device.HasVertexViewportLayer(),
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} {
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if (use_asynchronous_shaders) {
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workers = CreateWorkers();
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@ -435,8 +435,8 @@ std::unique_ptr<GraphicsPipeline> ShaderCache::CreateGraphicsPipeline(
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index == static_cast<u32>(Maxwell::ShaderType::Geometry);
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if (key.unique_hashes[index] == 0 && is_emulated_stage) {
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auto topology = MaxwellToOutputTopology(key.gs_input_topology);
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programs[index] = GenerateLayerPassthrough(pools.inst, pools.block, host_info,
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*layer_source_program, topology);
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programs[index] = GenerateGeometryPassthrough(pools.inst, pools.block, host_info,
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*layer_source_program, topology);
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continue;
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}
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if (key.unique_hashes[index] == 0) {
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@ -467,7 +467,7 @@ std::unique_ptr<GraphicsPipeline> ShaderCache::CreateGraphicsPipeline(
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programs[index] = MergeDualVertexPrograms(program_va, program_vb, env);
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}
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if (programs[index].requires_layer_emulation) {
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if (programs[index].info.requires_layer_emulation) {
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layer_source_program = &programs[index];
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}
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}
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@ -46,7 +46,7 @@ MICROPROFILE_DECLARE(Vulkan_PipelineCache);
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namespace {
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using Shader::Backend::SPIRV::EmitSPIRV;
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using Shader::Maxwell::ConvertLegacyToGeneric;
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using Shader::Maxwell::GenerateLayerPassthrough;
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using Shader::Maxwell::GenerateGeometryPassthrough;
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using Shader::Maxwell::MergeDualVertexPrograms;
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using Shader::Maxwell::TranslateProgram;
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using VideoCommon::ComputeEnvironment;
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@ -339,7 +339,7 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, const Device& device
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.needs_demote_reorder = driver_id == VK_DRIVER_ID_AMD_PROPRIETARY_KHR ||
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driver_id == VK_DRIVER_ID_AMD_OPEN_SOURCE_KHR,
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.support_snorm_render_buffer = true,
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.requires_layer_emulation = !device.IsExtShaderViewportIndexLayerSupported(),
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.support_viewport_index_layer = device.IsExtShaderViewportIndexLayerSupported(),
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};
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}
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@ -531,8 +531,8 @@ std::unique_ptr<GraphicsPipeline> PipelineCache::CreateGraphicsPipeline(
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index == static_cast<u32>(Maxwell::ShaderType::Geometry);
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if (key.unique_hashes[index] == 0 && is_emulated_stage) {
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auto topology = MaxwellToOutputTopology(key.state.topology);
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programs[index] = GenerateLayerPassthrough(pools.inst, pools.block, host_info,
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*layer_source_program, topology);
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programs[index] = GenerateGeometryPassthrough(pools.inst, pools.block, host_info,
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*layer_source_program, topology);
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continue;
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}
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if (key.unique_hashes[index] == 0) {
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@ -556,7 +556,7 @@ std::unique_ptr<GraphicsPipeline> PipelineCache::CreateGraphicsPipeline(
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programs[index] = MergeDualVertexPrograms(program_va, program_vb, env);
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}
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if (programs[index].requires_layer_emulation) {
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if (programs[index].info.requires_layer_emulation) {
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layer_source_program = &programs[index];
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}
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}
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