early-access version 3122

This commit is contained in:
pineappleEA 2022-11-17 18:04:39 +01:00
parent 93e762376a
commit d9c91acc73
14 changed files with 41 additions and 14 deletions

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@ -1,7 +1,7 @@
yuzu emulator early access yuzu emulator early access
============= =============
This is the source code for early-access 3121. This is the source code for early-access 3122.
## Legal Notice ## Legal Notice

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@ -320,6 +320,7 @@ void SetupOptions(const IR::Program& program, const Profile& profile,
} }
if (stage == Stage::Fragment) { if (stage == Stage::Fragment) {
header += "OPTION ARB_draw_buffers;"; header += "OPTION ARB_draw_buffers;";
header += "OPTION ARB_fragment_layer_viewport;";
} }
} }

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@ -104,6 +104,9 @@ void EmitGetAttribute(EmitContext& ctx, IR::Inst& inst, IR::Attribute attr, Scal
case IR::Attribute::PrimitiveId: case IR::Attribute::PrimitiveId:
ctx.Add("MOV.F {}.x,primitive.id;", inst); ctx.Add("MOV.F {}.x,primitive.id;", inst);
break; break;
case IR::Attribute::Layer:
ctx.Add("MOV.F {}.x,fragment.layer;", inst);
break;
case IR::Attribute::PositionX: case IR::Attribute::PositionX:
case IR::Attribute::PositionY: case IR::Attribute::PositionY:
case IR::Attribute::PositionZ: case IR::Attribute::PositionZ:

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@ -205,6 +205,9 @@ void EmitGetAttribute(EmitContext& ctx, IR::Inst& inst, IR::Attribute attr,
case IR::Attribute::PrimitiveId: case IR::Attribute::PrimitiveId:
ctx.AddF32("{}=itof(gl_PrimitiveID);", inst); ctx.AddF32("{}=itof(gl_PrimitiveID);", inst);
break; break;
case IR::Attribute::Layer:
ctx.AddF32("{}=itof(gl_Layer);", inst);
break;
case IR::Attribute::PositionX: case IR::Attribute::PositionX:
case IR::Attribute::PositionY: case IR::Attribute::PositionY:
case IR::Attribute::PositionZ: case IR::Attribute::PositionZ:

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@ -315,6 +315,8 @@ Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, Id vertex) {
switch (attr) { switch (attr) {
case IR::Attribute::PrimitiveId: case IR::Attribute::PrimitiveId:
return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.primitive_id)); return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.primitive_id));
case IR::Attribute::Layer:
return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.layer));
case IR::Attribute::PositionX: case IR::Attribute::PositionX:
case IR::Attribute::PositionY: case IR::Attribute::PositionY:
case IR::Attribute::PositionZ: case IR::Attribute::PositionZ:

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@ -1359,6 +1359,10 @@ void EmitContext::DefineInputs(const IR::Program& program) {
if (loads[IR::Attribute::PrimitiveId]) { if (loads[IR::Attribute::PrimitiveId]) {
primitive_id = DefineInput(*this, U32[1], false, spv::BuiltIn::PrimitiveId); primitive_id = DefineInput(*this, U32[1], false, spv::BuiltIn::PrimitiveId);
} }
if (loads[IR::Attribute::Layer]) {
AddCapability(spv::Capability::Geometry);
layer = DefineInput(*this, U32[1], false, spv::BuiltIn::Layer);
}
if (loads.AnyComponent(IR::Attribute::PositionX)) { if (loads.AnyComponent(IR::Attribute::PositionX)) {
const bool is_fragment{stage != Stage::Fragment}; const bool is_fragment{stage != Stage::Fragment};
const spv::BuiltIn built_in{is_fragment ? spv::BuiltIn::Position : spv::BuiltIn::FragCoord}; const spv::BuiltIn built_in{is_fragment ? spv::BuiltIn::Position : spv::BuiltIn::FragCoord};

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@ -232,7 +232,7 @@ void Maxwell3D::ProcessMethodCall(u32 method, u32 argument, u32 nonshadow_argume
use_topology_override = true; use_topology_override = true;
return; return;
case MAXWELL3D_REG_INDEX(clear_surface): case MAXWELL3D_REG_INDEX(clear_surface):
return ProcessClearBuffers(); return ProcessClearBuffers(1);
case MAXWELL3D_REG_INDEX(report_semaphore.query): case MAXWELL3D_REG_INDEX(report_semaphore.query):
return ProcessQueryGet(); return ProcessQueryGet();
case MAXWELL3D_REG_INDEX(render_enable.mode): case MAXWELL3D_REG_INDEX(render_enable.mode):
@ -596,8 +596,8 @@ u32 Maxwell3D::GetRegisterValue(u32 method) const {
return regs.reg_array[method]; return regs.reg_array[method];
} }
void Maxwell3D::ProcessClearBuffers() { void Maxwell3D::ProcessClearBuffers(u32 layer_count) {
rasterizer->Clear(); rasterizer->Clear(layer_count);
} }
void Maxwell3D::ProcessDraw(u32 instance_count) { void Maxwell3D::ProcessDraw(u32 instance_count) {

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@ -3086,6 +3086,9 @@ public:
std::vector<u8> inline_index_draw_indexes; std::vector<u8> inline_index_draw_indexes;
/// Handles a write to the CLEAR_BUFFERS register.
void ProcessClearBuffers(u32 layer_count);
private: private:
void InitializeRegisterDefaults(); void InitializeRegisterDefaults();
@ -3120,9 +3123,6 @@ private:
/// Handles firmware blob 4 /// Handles firmware blob 4
void ProcessFirmwareCall4(); void ProcessFirmwareCall4();
/// Handles a write to the CLEAR_BUFFERS register.
void ProcessClearBuffers();
/// Handles a write to the QUERY_GET register. /// Handles a write to the QUERY_GET register.
void ProcessQueryGet(); void ProcessQueryGet();

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@ -126,11 +126,25 @@ void HLE_3F5E74B9C9A50164(Engines::Maxwell3D& maxwell3d, const std::vector<u32>&
} }
} }
constexpr std::array<std::pair<u64, HLEFunction>, 4> hle_funcs{{ // Multi-layer Clear
void HLE_EAD26C3E2109B06B(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters) {
ASSERT(parameters.size() == 1);
const Engines::Maxwell3D::Regs::ClearSurface clear_params{parameters[0]};
const u32 rt_index = clear_params.RT;
const u32 num_layers = maxwell3d.regs.rt[rt_index].depth;
ASSERT(clear_params.layer == 0);
maxwell3d.regs.clear_surface.raw = clear_params.raw;
maxwell3d.ProcessClearBuffers(num_layers);
}
constexpr std::array<std::pair<u64, HLEFunction>, 5> hle_funcs{{
{0x771BB18C62444DA0, &HLE_771BB18C62444DA0}, {0x771BB18C62444DA0, &HLE_771BB18C62444DA0},
{0x0D61FC9FAAC9FCAD, &HLE_0D61FC9FAAC9FCAD}, {0x0D61FC9FAAC9FCAD, &HLE_0D61FC9FAAC9FCAD},
{0x0217920100488FF7, &HLE_0217920100488FF7}, {0x0217920100488FF7, &HLE_0217920100488FF7},
{0x3F5E74B9C9A50164, &HLE_3F5E74B9C9A50164}, {0x3F5E74B9C9A50164, &HLE_3F5E74B9C9A50164},
{0xEAD26C3E2109B06B, &HLE_EAD26C3E2109B06B},
}}; }};
class HLEMacroImpl final : public CachedMacro { class HLEMacroImpl final : public CachedMacro {

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@ -43,7 +43,7 @@ public:
virtual void Draw(bool is_indexed, u32 instance_count) = 0; virtual void Draw(bool is_indexed, u32 instance_count) = 0;
/// Clear the current framebuffer /// Clear the current framebuffer
virtual void Clear() = 0; virtual void Clear(u32 layer_count) = 0;
/// Dispatches a compute shader invocation /// Dispatches a compute shader invocation
virtual void DispatchCompute() = 0; virtual void DispatchCompute() = 0;

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@ -136,7 +136,7 @@ void RasterizerOpenGL::LoadDiskResources(u64 title_id, std::stop_token stop_load
shader_cache.LoadDiskResources(title_id, stop_loading, callback); shader_cache.LoadDiskResources(title_id, stop_loading, callback);
} }
void RasterizerOpenGL::Clear() { void RasterizerOpenGL::Clear(u32 layer_count) {
MICROPROFILE_SCOPE(OpenGL_Clears); MICROPROFILE_SCOPE(OpenGL_Clears);
if (!maxwell3d->ShouldExecute()) { if (!maxwell3d->ShouldExecute()) {
return; return;

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@ -69,7 +69,7 @@ public:
~RasterizerOpenGL() override; ~RasterizerOpenGL() override;
void Draw(bool is_indexed, u32 instance_count) override; void Draw(bool is_indexed, u32 instance_count) override;
void Clear() override; void Clear(u32 layer_count) override;
void DispatchCompute() override; void DispatchCompute() override;
void ResetCounter(VideoCore::QueryType type) override; void ResetCounter(VideoCore::QueryType type) override;
void Query(GPUVAddr gpu_addr, VideoCore::QueryType type, std::optional<u64> timestamp) override; void Query(GPUVAddr gpu_addr, VideoCore::QueryType type, std::optional<u64> timestamp) override;

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@ -213,7 +213,7 @@ void RasterizerVulkan::Draw(bool is_indexed, u32 instance_count) {
EndTransformFeedback(); EndTransformFeedback();
} }
void RasterizerVulkan::Clear() { void RasterizerVulkan::Clear(u32 layer_count) {
MICROPROFILE_SCOPE(Vulkan_Clearing); MICROPROFILE_SCOPE(Vulkan_Clearing);
if (!maxwell3d->ShouldExecute()) { if (!maxwell3d->ShouldExecute()) {
@ -256,7 +256,7 @@ void RasterizerVulkan::Clear() {
.rect = regs.clear_control.use_scissor ? GetScissorState(regs, 0, up_scale, down_shift) .rect = regs.clear_control.use_scissor ? GetScissorState(regs, 0, up_scale, down_shift)
: default_scissor, : default_scissor,
.baseArrayLayer = regs.clear_surface.layer, .baseArrayLayer = regs.clear_surface.layer,
.layerCount = 1, .layerCount = layer_count,
}; };
if (clear_rect.rect.extent.width == 0 || clear_rect.rect.extent.height == 0) { if (clear_rect.rect.extent.width == 0 || clear_rect.rect.extent.height == 0) {
return; return;

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@ -65,7 +65,7 @@ public:
~RasterizerVulkan() override; ~RasterizerVulkan() override;
void Draw(bool is_indexed, u32 instance_count) override; void Draw(bool is_indexed, u32 instance_count) override;
void Clear() override; void Clear(u32 layer_count) override;
void DispatchCompute() override; void DispatchCompute() override;
void ResetCounter(VideoCore::QueryType type) override; void ResetCounter(VideoCore::QueryType type) override;
void Query(GPUVAddr gpu_addr, VideoCore::QueryType type, std::optional<u64> timestamp) override; void Query(GPUVAddr gpu_addr, VideoCore::QueryType type, std::optional<u64> timestamp) override;